I did a RAM upgrade for the Prophet 3000 a few years back. Unfortunately, it didn’t work correctly, and I didn’t have the motivation or the time to figure out why. It was strange in that it would fail some tests and pass others.
To give a bit of background, the Prophet 3000 has several custom chips. Two of them, the “I-627” (voice controller) and “I-628” (DMA controller) share control of the sample memory. The I-627 plays back samples and the I-628 transfers samples from SCSI or the main processor to sample memory. The diagnostics let you run memory tests with either the I-627 or I-628 controlling the test. The board I built was passing the I-627 tests but failing the I-628 tests. I figured that the problem was somehow timing related but I decided to shelve the project.
A few months ago a friend purchased a beat-up P3000 that had been in a storage shed for years, and asked me to restore it. After many hours of ultrasonic cleaning, rust removal bath, IC socket replacement, re-capping, and replacing regulators and a few defective parts, it was up and running again. I decided to revisit the memory board issue. I used a logic probe to look at the memory timing and discovered that the I-628 is much more sensitive to timing than the I-627. The memory address and data buses are multiplexed and the address bus itself is multiplexed. Therefore, the 16 lines share three pieces of information: address row, address column, and data. Two other lines, RAS and CAS, go active as these transitions take place. What happens with the I-628 is that the address row and column transitions are too close to the RAS and CAS signals. Memory chips have a “setup time” where the address has to be valid for a certain period (usually a few nanoseconds) before the corresponding RAS or CAS signal activates. The onboard P3000 memory has IC buffers that add a bit of delay for these signals, and my board was lacking those. I had assumed that the buffers were there to reduce the load on the sample memory bus, but it was also adding the necessary delay.
I modified my design with simple logic gates to buffer the RAS, CAS, and memory read and write signals and got a few test boards made by OSH Park. And now it tests perfectly.
I also discovered that certain brands of RAM fail the memory tests due to out of spec timing (this is the RAM that goes in the expansion sockets on the motherboard). Hitachi was OK, the original AT&T RAM was OK, but Mitsubishi would fail testing after a while (due to heating up, I guess).
And finally, none of this would be possible without a new I-627 rev B chip. I made an adapter for the first generation P3000’s with the PGA style I-627 to enable fitting the PLCC package I-627B. The original I-627A couldn’t deal with more that one bank of RAM for some reason. Unfortunately Wine Country seems to have stopped selling the I-627B’s, so at this time the only P3000’s that can be upgraded are the second generation.
Do you know how to distinguish first and second generation units? I’d like to know about mine…
Just found your site Tom after (sadly) pulling my P3000 out of the dustbin. I need to get the thing working again and was also interested in doing a memory upgrade to 8MB. I’ve got a “B” machine with 4MB already, so maybe 8MB is workable. And yeah- staring at schematics, that multiplexed data/row/column “R” bus just looks nasty. Interesting on the timing and that that’s why they’ve got those octal buffers sprinkled all over. I was considering trying to do a design using SIMMs instead of discrete chips but the multiplexed bus likely shoots that one down.