Well, it turns out that the daughterboard had a LOT more problems than I would have liked. On the hardware side, solder bridges and shorts took a lot of time to track down. Also, similar to the main board, the main CPU’s ASTB (address strobe) signal needs to be buffered, as it’s not latching the address bits properly on its own.
Also a couple of dumb errors with the CPLD. I had several versions of the project, and the version I used had the pin placement wrong. Also had the decode logic wrong for the Flash ROM.
The good news is that Jim is working with the new hardware and I think we may see results in a couple of weeks.
Aside from this project, I’ve made some progress on the new revision of the main CPU board. All of the TTL logic is being replaced with two medium-sized CPLD’s and it will have a newer floppy controller and the VNC1L USB controller integrated.